1. Field of the Invention
The invention relates to a phase interpolation circuit. Particularly, the invention relates to a phase interpolation circuit capable of generating a differential output signal with 50% of duty cycle.
2. Description of Related Art
In a high-speed transmission interface module (for example, a universal serial bus (USB) 3.0 interface module), a clock and data recovery circuit is generally configured to recover signals containing noise components, where a phase interpolation circuit is a core circuit composing the clock and data recovery circuit. Therefore, it is an important issue to ameliorate the phase interpolation circuit to improve whole performance of the clock and data recovery circuit.
Generally, the phase interpolation circuit can be implemented through current mode logic to cope with the requirement of a high-speed transmission. However, the phase interpolation circuit of the current mode logic has following disadvantages: (1) a linearity thereof is liable to be influenced by a parasitic capacitance and a front-end circuit load, so that a duty cycle of an output signal has a great variation, especially under an influence of process variation; (2) it is of no avail for low-voltage operations, which leads to a limited operating range.
Therefore, how to adjust the duty cycle of the output signal or implement the low-voltage operations is an important issue to be developed in design of the phase interpolation circuit.